ASAP-1

ASAP-1 Main Page

ARC-lite

ARC-lite Main Page

INFRATEC-1

INFRATEC-1  Main Page

ULTRASPEC-III

ULTRASPEC-III Main Page

We are pleased to present you with a Video Tutorial to illustrate the standard backside preparation of a packaged part with ASAP-1 and ARC-lite.

Total run time for the video sequence is around 21 minutes. To view any of the videos, simply click on the center of the screen.

The sample used during the video sequence is a leadless plastic package, which requires all six main preparation steps to achieve a decapped, thinned and polished part. Total process time for such a part is 45 minutes to 1 hour.

ASAP-1 is capable of preparing a wide range of wafer, die and package level devices - ask us how we can help with the processing of your specific parts. Click here to see an Applications Array

Part 1 - Introduction

Part 2 - The Main Controls on ASAP-1

Part 3- Analyzing Cross-sections - Preparing for successful Selected Area Preparation

Part 4 - (No video) Mounting a part on the sample mounting plate

Note: As you can see from other parts of the video, the leadless package is mounted here with Crystal Wax adhesive, which melts at 78C and can be painted onto the sample or plate.

Part 5 - Positioning part on machine and setting up ASAP-1 for polishing

Note: Not shown in the video is the Amplitude Setting Indicator which is used on both the X and Y stages to achieve the correct amplitude for the cavity size required, to an accuracy of 10 microns - See image below.

Part 6 - STEP 1 - Decapsulation of the Plastic Package Material

Note : ULTRA TEC offers all out tool types in several sizes from 1mm to 5mm. This allows the process to be optimized for the cavity required (from the smallest surface mount device, to the largest flip chip). For specialist applications, we also offer 0.4mm and 0.7mm diameter tools.

Part 7 - STEP 2 - Removing the Copper paddle/ heat sink

Note : Step 2 is the only step in the preparation sequence, in which you should lock the ASAP-1 polishing head.

Part 8 - STEP 3 - Silicon Thinning

Part 9 - STEP 4 - Pre-polishing

Part 10 - STEP 5 - Intermediate Polishing

Part 11 - STEP 6 - Final Polishing

Note : The image below shows the part after final polishing.

Part 12 - AR Coating

Part 13 - Backside Imaging

Note 1: Shown on the video are the imaging results of our INFRATEC-1 Backside microscope (20X objective), in conjunction with ULTRASPEC-III laser illuminator.

Note 2: We hope you spotted the deliberate mistake on the commentary for this video! Heavily-doped silicon such as is seen in many packaged devices needs to be thinned to less than 100 microns to achieve sufficient transparency for backside imaging. ASAP-1 is routinely used to achieve 50 microns or less. 

Part 14 - ULTRACOLLIMATOR

Note: ULTRACOLLIMATOR is an available accessory for many of ULTRA TEC's key polishing systems. It allows for greatly increased accuracy of parallelism, leading to improved surface flatness and improved use for analysis.

Thanks for your time in taking the tutorial. We hope you found this information useful for your understanding of the backside sample preparation of electronic devices.

To optimize the polishing of your own parts, please contact us for suggestions on a customized process route.

For more information on any of the products discussed in this tutorial, please click on the links to the left, or e-mail us on info@ultratecusa.com